Altera Corporation was an American manufacturer of programmable logic devices (PLDs), reconfigurable complex digital circuits. The company released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs, Quartus II design software, and Enpirion PowerSoC DC-DC power solutions.

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Altera

Category: Content
Type: Blog Article

Generated 6 days ago

Altera

Category: Content
Type: Blog Article

Generated 1 week ago

Altera

Category: Content
Type: Blog Article

Generated 2 weeks ago

Altera

Category: Content
Type: Youtube Video

Generated 3 weeks ago

Altera

Category: Content
Type: Youtube Video

Generated 3 weeks ago

New YouTube videos detected.

  • Arria 10 中创建简单的温度感应设计

    This video demonstrates how to create a simple temperature sensing design for debug use. The design will involve ISSP for control and JTAG interfacing for signal tap to monitor the data. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions.

Altera

Category: Content
Type: Youtube Video

Generated 3 weeks ago

New YouTube videos detected.

  • 使用 Arria 10 Native PHY 中的系统控制台读取融合 DFE tap 值

    This video will show the user how to read the converged DFE tap values in the Arria 10 Native PHY using system console. DFE compensates for inter-symbol interference (ISI). It can help to improve the RX signal integrity performance in a transceiver link. In adaptive mode, the DFE tap values are controlled by the Adaptive Parametric Tuning Engine and will converge to specific values. This video wil...

Altera

Category: Content
Type: Youtube Video

Generated 3 weeks ago

New YouTube videos detected.

  • 使用 Arria 10 嵌入式流转化器和重配置配置文件切换 CDR refclk

    This video will show the users how to perform dynamic reconfiguration to switch the CDR refclks with the embedded streamer and multiple reconfiguration profiles in an Arria 10 device. Dynamic CDR refclk switching enables the transceiver RX channel to support different data rates without the need to re-program the device. This video will cover the IP required, IP configuration and a Modelsim simula...

Altera

Category: Content
Type: Youtube Video

Generated 3 weeks ago

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New YouTube videos detected.

  • programmed for success

    See how Altera and Intel are energizing the FPGA industry with innovative product advancements and improved product execution - at the same support levels you've come expect. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New YouTube videos detected.

  • Design for Intel FPGA's with Quartus Prime

    Quartus® Prime design software includes everything you need to design for Intel® FPGAs, SoCs, and CPLDs from design entry and synthesis to optimization, verification, and simulation. The Quartus Prime Pro Edition software supports the advanced features in Intel's next-generation FPGAs and SoCs, starting with the Arria® 10 device family. Watch videos below to learn more about the new features in v1...

Altera

Category: Content
Type: Blog Article

Generated 1 month ago

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New YouTube videos detected.

  • Enabling reverse serial pre-CDR loopback in Stratix V GT Native PHY IP using dynamic reconfiguration

    This video will show the user how to enable the reverse serial pre-CDR loopback mode in the Stratix V GT transceiver using dynamic reconfiguration and perform a link test in Modelsim simulation. Reverse serial pre-CDR loopback mode is generally used in transceiver hardware debugging to isolate issues due to external data source. This video will cover IPs required, IP configuration and Modelsim sim...

Altera

Category: Content
Type: Youtube Video

Generated 1 month ago

New YouTube videos detected.

  • Simulating Arria 10 RLDRAM3 using the vendor memory model

    This video will show the user how to run an example design simulation by to replacing Intel PSG's generic memory model with the vendor memory model. Intel PSG's design example is generated with a generic memory model for simulation, but one might wish to replace the generic memory model with the vendor's memory model to exactly match the memory device that they are using on their board.

Altera

Category: Content
Type: Blog Article

Generated 2 months ago

Altera

Category: Content
Type: Youtube Video

Generated 2 months ago

Altera

Category: Content
Type: Youtube Video

Generated 2 months ago

New YouTube videos detected.

  • Meeting FPGA Requirements with Enpirion® Power Solutions

    Start your FPGA power design the right way by maximizing your system performance, while meeting the most stringent power, budget, and solution size requirements needed for an FPGA with the EM2130. Learn more about Enpirion Power solutions: http://bit.ly/2numSLJ Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Youtube Video

Generated 2 months ago

New YouTube videos detected.

  • Getting Started with EM2130

    Get an overview of how easy it is to power any programming logic device with the EM2130 Eval kit’s default configuration. Learn more about Enpirion Power solutions: http://bit.ly/2numSLJ Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Youtube Video

Generated 2 months ago

New YouTube videos detected.

  • Creating Custom Configurations on the EM21xx PowerSoCs to suit any application

    Using the Intel Enpirion Digital Power Configurator GUI, learn how to generate a custom configuration and a programming file with a simple example. Learn more about Enpirion Power solutions: http://bit.ly/2numSLJ Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

Altera

Category: Content
Type: Blog Article

Generated 2 months ago

Altera

Category: Content
Type: Youtube Video

Generated 2 months ago

New YouTube videos detected.

  • Switching the CDR reference clock source on Arria 10 FPGAs

    This video will show the users how to perform dynamic reconfiguration to switch the CDR refclks with the embedded streamer and multiple reconfiguration profiles in an Arria 10 device. Dynamic CDR refclk switching enables the transceiver RX channel to support different data rates without the need to re-program the device. This video will cover the IP required, IP configuration and a Modelsim simula...

Altera

Category: Content
Type: Blog Article

Generated 2 months ago

Altera

Category: Content
Type: Youtube Video

Generated 2 months ago

New YouTube videos detected.

  • 如何在 Arria 10 中实现 IO 锁相环 (PLL) 重配置

    This video shows you how to implement IOPLL reconfiguration in an Arria 10 FPGA. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • 如何在 Arria 10 中实现 IO 锁相环 (PLL) 动态相移

    This video shows you how to implement the IOPLL dynamic phase shift feature in an Arria 10 FPGA. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga

  • 创建 UEFI LCD 应用程序、运行 LCD 应用程序(第二部分)

    The Altera Arria 10 SoC UEFI Bootloader "make app" feature is enabled in the UEFI Shell i.e. after the post DDR boot stage, known as UEFI DXE Phase. It is one of the extended UEFI functionality which allows user to access to a broad range of pre-existing UEFI utility already developed by the open source community. Prior to booting the DXE phase, it will requires DDR SDRAM to be ready. Part 2 of 2...

  • 创建 UEFI LCD 应用程序、运行 LCD 应用程序(第一部分)

    The Altera Arria 10 SoC UEFI Bootloader "make app" feature is enabled in the UEFI Shell i.e. after the post DDR boot stage, known as UEFI DXE Phase. It is one of the extended UEFI functionality which allows user to access to a broad range of pre-existing UEFI utility already developed by the open source community. Prior to booting the DXE phase, it will requires DDR SDRAM to be ready. Part 1 of 2 ...

Altera

Category: Content
Type: Blog Article

Generated 3 months ago

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